The present disclosure relates to the field of semiconductor fabrication, and more specifically, to threshold voltage tuning for fin field effect transistors (finFET) on a substrate while reducing performance penalties due to the tuning.
Integrated circuits (ICs) can include large numbers of devices on a single substrate. As the number of devices formed per IC substrate and the density of the devices on the substrate increases, the dimensions of the individual devices drops significantly. In particular, the dimensions of gate thickness and channel separation of source and drain elements of field effect transistor (FET) devices may be reduced such that there are only micrometer and nanometer separations of the source, drain, and gate in the substrate. Although devices are being steadily reduced in size, the performance characteristics of the devices must be maintained or improved. In addition to performance characteristics, performance reliability, and durability of devices, manufacturing reliability and cost are also critical.
Several problems can arise with the miniaturization of devices, including short channel effects, punch-through, and current leakage. These problems affect both the performance of the devices and the manufacturing process. The impact of short channel effects on device performance is seen in a reduction in the device threshold voltage and an increase of sub-threshold current. More particularly, as the channel length becomes smaller, the source and drain depletion regions get closer to each other. The depletion regions may essentially occupy the entire channel area between the source and drain. As a result of this effective occupation of the channel area by the source and drain depletion regions, the channel is in part depleted and the gate charge necessary to alter the source and drain current flow is reduced.
A finFET is a type of field effect transistor structure that exhibits reduced short channel effects. In a finFET structure, the channel is formed as a vertical silicon fin structure on top of a substrate, with the gate also being located in the fin structure on top of the channel. A finFET may be formed on an undoped or low-doped substrate. FinFETs can have superior carrier mobility, due to lowered effective field (Eeff) and reduced carrier scattering. A finFET structure may also alleviate random dopant fluctuation (RDF) at relatively small devices dimensions as compared to a standard FET.
Depending on the application for which an IC chip is used, finFETs having different threshold voltages (Vt) may need to be present in the IC. However, variation of the threshold voltages across a large number of finFETs on a single substrate may present difficulties. The threshold voltage may be modulated by tuning the finFET gate stack work functions, but gate stack patterning to tune the work functions in gate-first finFET fabrication is challenging, and the choice of gate metals that results in different work functions that may be used in gate-last processing is relatively limited. Furthermore, carrier mobility, effective channel length and overlap capacitance can be adversely affected.